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| author | Igor Breger <igor.breger@intel.com> | 2017-06-20 09:15:10 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2017-06-20 09:15:10 +0000 |
| commit | 1dcd5e8dc8274ede357868577abd7ac32f9b3bd9 (patch) | |
| tree | 5268e52fc26c04d296e0695d85f04d9a16f38ffa /lldb/scripts/Python | |
| parent | 14535f0fc2978338071818dd2701e70ac4917126 (diff) | |
| download | llvm-1dcd5e8dc8274ede357868577abd7ac32f9b3bd9.zip llvm-1dcd5e8dc8274ede357868577abd7ac32f9b3bd9.tar.gz llvm-1dcd5e8dc8274ede357868577abd7ac32f9b3bd9.tar.bz2 | |
[GlobalISel][X86] Get correct RegClass for given RegBank.
Summary:
In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available.
Split from https://reviews.llvm.org/D33665
Reviewers: qcolombet, t.p.northover, zvi, guyblank
Reviewed By: t.p.northover, guyblank
Subscribers: guyblank, rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D33952
Conflicts:
test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
llvm-svn: 305784
Diffstat (limited to 'lldb/scripts/Python')
0 files changed, 0 insertions, 0 deletions