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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-08 10:04:41 -0700 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2019-10-25 13:11:09 -0700 |
| commit | 171cf5302f43776b07615e32b2ffd6ddf4e5d890 (patch) | |
| tree | 1f029fd31e417dba705e7fbfd15469fbb8f8a683 /lldb/scripts/Python/python-wrapper.swig | |
| parent | 1ce552f3ef8d6455c10a9886191c1898594975e0 (diff) | |
| download | llvm-171cf5302f43776b07615e32b2ffd6ddf4e5d890.zip llvm-171cf5302f43776b07615e32b2ffd6ddf4e5d890.tar.gz llvm-171cf5302f43776b07615e32b2ffd6ddf4e5d890.tar.bz2 | |
AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
Custom lower this to a target instruction with the merge operands. I
think it might be better to directly select this and emit a
REG_SEQUENCE, but this would be more work since it would require
splitting the tablegen patterns for these cases from the other
atomics.
Diffstat (limited to 'lldb/scripts/Python/python-wrapper.swig')
0 files changed, 0 insertions, 0 deletions