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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2012-10-10 21:25:01 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2012-10-10 21:25:01 +0000 |
| commit | b9bc47409d8ae8f7e1b1652e95ccb1ea29497476 (patch) | |
| tree | 7681b90e6142687a59880e16aad5be471f858f73 /lldb/scripts/Python/python-extensions.swig | |
| parent | 38d945872097549606ea62b64ded743afdab0648 (diff) | |
| download | llvm-b9bc47409d8ae8f7e1b1652e95ccb1ea29497476.zip llvm-b9bc47409d8ae8f7e1b1652e95ccb1ea29497476.tar.gz llvm-b9bc47409d8ae8f7e1b1652e95ccb1ea29497476.tar.bz2 | |
When generating spill and reload code for vector registers on PowerPC,
the compiler makes use of GPR0. However, there are two flavors of
GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0
(X0). The spill/reload code makes use of R0 regardless of whether we
are generating 32- or 64-bit code.
This patch corrects the problem in the obvious manner, using X0 and
ADDI8 for 64-bit and R0 and ADDI for 32-bit.
llvm-svn: 165658
Diffstat (limited to 'lldb/scripts/Python/python-extensions.swig')
0 files changed, 0 insertions, 0 deletions