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| author | Craig Topper <craig.topper@sifive.com> | 2024-08-14 08:44:57 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-14 08:44:57 -0700 |
| commit | abc1acf8df3b212a03650c314b7832b3aa7ccd42 (patch) | |
| tree | 6d1dc476d9b30e41aacde9c6559f6665b11f9c63 /libcxx | |
| parent | 294ed6a1eb090627441ee0426a64d8f71985fce3 (diff) | |
| download | llvm-abc1acf8df3b212a03650c314b7832b3aa7ccd42.zip llvm-abc1acf8df3b212a03650c314b7832b3aa7ccd42.tar.gz llvm-abc1acf8df3b212a03650c314b7832b3aa7ccd42.tar.bz2 | |
[TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (#101751)
If the upper bits of the shr aren't demanded.
This helps with cases where the outer srl was originally an sra and was
converted to a srl by SimplifyDemandedBits before it had a chance to
combine with the inner sra. This can occur when the inner sra was part
of a sign_extend_inreg expansion.
There are some regressions in ARM and Thumb2.
Diffstat (limited to 'libcxx')
0 files changed, 0 insertions, 0 deletions