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| author | Moritz Roth <moritz.roth@arm.com> | 2014-08-15 17:00:30 +0000 |
|---|---|---|
| committer | Moritz Roth <moritz.roth@arm.com> | 2014-08-15 17:00:30 +0000 |
| commit | 8f3765625e177b0795ca2daac38d392c9c7f2179 (patch) | |
| tree | c47cd9f5abdb749ee0b22155acb7d89a2dfaf27b /libcxx/src/algorithm.cpp | |
| parent | 378a43bfe0a03e89b26c2e10247671e89ac24bfb (diff) | |
| download | llvm-8f3765625e177b0795ca2daac38d392c9c7f2179.zip llvm-8f3765625e177b0795ca2daac38d392c9c7f2179.tar.gz llvm-8f3765625e177b0795ca2daac38d392c9c7f2179.tar.bz2 | |
ARM: Fix and re-enable load/store optimizer for Thumb1.
In a previous iteration of the pass, we would try to compensate for
writeback by updating later instructions and/or inserting a SUBS to
reset the base register if necessary.
Since such a SUBS sets the condition flags it's not generally safe to do
this. For now, only merge LDR/STRs if there is no writeback to the base
register (LDM that loads into the base register) or the base register is
killed by one of the merged instructions. These cases are clear wins
both in terms of instruction count and performance.
Also add three new test cases, and update the existing ones accordingly.
llvm-svn: 215729
Diffstat (limited to 'libcxx/src/algorithm.cpp')
0 files changed, 0 insertions, 0 deletions