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| author | Alexander Richardson <alexrichardson@google.com> | 2026-02-18 17:23:10 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-02-18 17:23:10 -0800 |
| commit | 3459bb4f279fa40f463cbfe19cf133a578359a99 (patch) | |
| tree | fa31a15024d6bfc7aff4f04313a2ef2c93deaac2 /libc/test/src/wchar/wcslcat_test.cpp | |
| parent | f9e002158c714362b4d87ceb27612825603d90b2 (diff) | |
| download | llvm-main.zip llvm-main.tar.gz llvm-main.tar.bz2 | |
This is useful for `InstAlias` where a fixed register may depend on the
HwMode. The motivating use case for this is the RISC-V RVY ISA where
certain instructions mnemonics are remapped to take a different
register class depending on the HwMode and can be used as follows:
```
def NullReg : RegisterByHwMode<PtrRC, [RV32I, RV64I, RV64Y, RV64Y],
[X0, X0, X0_Y, X0_Y]>;
```
Pull Request: https://github.com/llvm/llvm-project/pull/175227
Diffstat (limited to 'libc/test/src/wchar/wcslcat_test.cpp')
0 files changed, 0 insertions, 0 deletions