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authorPankaj Dwivedi <pankajkumar.divedi@amd.com>2026-02-19 11:08:44 +0530
committerGitHub <noreply@github.com>2026-02-19 11:08:44 +0530
commitfafedcd44eabacb7ecc10445b5b8058569985022 (patch)
treebb61796635331224a3b2dfb8531a8e5c3b55a925 /libc/test/src/wchar/mbsnrtowcs_test.cpp
parent3e3713c2f589c474c24d09ebdc310cacf08b2f40 (diff)
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[AMDGPU][GlobalISel][NFC] Filter getCandidatesForLowering to only process G_PHI (#181814)HEADmain
The divergence-lowering pass runs in three stages: 1. lowerTemporalDivergence() 2. lowerTemporalDivergenceI1() — creates PHI instructions via SSAUpdater 3. lowerPhis() — lowers divergent i1 G_PHIs into lane mask PHIs getCandidatesForLowering() in stage 3 iterates over all PHIs via MBB.phis() and checks isDivergent() on their destination registers. This includes PHI instructions already created by stage 2, whose registers were never part of the original uniformity analysis. Today, this works by accident — isDivergent() returns false for unknown registers, so these PHIs are skipped. But this relies on isDivergent() behavior for unanalyzed registers, which is not guaranteed. If isDivergent() were to return true for unknown registers (e.g., as a conservative default), lowerPhis() would re-process already-lowered PHIs, adding redundant COPY instructions(EX: https://github.com/llvm/llvm-project/pull/180509). This would not be a correctness issue, but would produce unnecessary code. Co-authored-by: padivedi <padivedi@amd.com>
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