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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2023-07-25 18:35:28 -0400 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2023-10-02 12:10:06 +0300 |
| commit | 32a23aecf8002e181eb1022b8733ef8666b3241f (patch) | |
| tree | ea9851494205708478dbe3f6c6f43bfdb80536fb /flang/lib/Frontend/CompilerInvocation.cpp | |
| parent | ffc67bb3602a6a9a4f886af362e1f2d7c9821570 (diff) | |
| download | llvm-32a23aecf8002e181eb1022b8733ef8666b3241f.zip llvm-32a23aecf8002e181eb1022b8733ef8666b3241f.tar.gz llvm-32a23aecf8002e181eb1022b8733ef8666b3241f.tar.bz2 | |
RegisterCoalescer: Forcibly leave SSA to avoid MIR test errors
Not sure how to produce a test that demonstrates the problem
today. The coalescer would have to introduce a verifier caught SSA
violation, like multiple defs of a virtual register. I'm not sure what
would do that now, but an upcoming patch will.
https://reviews.llvm.org/D156271
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions