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| author | SpencerAbson <Spencer.Abson@arm.com> | 2024-10-29 16:55:19 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-29 16:55:19 +0000 |
| commit | 2a9dd8af5ad9783d8ecba6bf93521de64bab6f81 (patch) | |
| tree | ffa65ff59dfe28742d98dfeb2f1ed06c3c369c88 /flang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 2ab98dfe19ac384f0cfac1a1fafc56b9dd7ad9b7 (diff) | |
| download | llvm-2a9dd8af5ad9783d8ecba6bf93521de64bab6f81.zip llvm-2a9dd8af5ad9783d8ecba6bf93521de64bab6f81.tar.gz llvm-2a9dd8af5ad9783d8ecba6bf93521de64bab6f81.tar.bz2 | |
[AArch64] Add assembly/disassembly for zeroing SVE FCVT{X} and BFCVT (#113916)
This patch adds assembly/disassembly support for the following SVE2.2
instructions
- FCVT (zeroing)
- FCVTX (zeroing)
- BFCVT (zeroing)
In accordance with:
https://developer.arm.com/documentation/ddi0602/2024-09/SVE-Instructions
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions