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authorDiego Caballero <dieg0ca6aller0@gmail.com>2024-11-20 20:57:39 -0800
committerGitHub <noreply@github.com>2024-11-20 20:57:39 -0800
commit32913724acf9e02beed46999fee1424086b8c884 (patch)
treeafbef80ae712097fdcef725cfc4c489b361a652d /clang/unittests/Serialization/InMemoryModuleCacheTest.cpp
parent197fb270cc2f947bdde047d9aac65b653f4f6f26 (diff)
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[mlir][vector] Fix 0-d vector transfer mask inference (#116526)
When inferring the mask of a transfer operation that results in a single `i1` element, we could represent it using either `vector<i1>` or vector<1xi1>. To avoid type mismatches, this PR updates the mask inference logic to consistently generate `vector<1xi1>` for these cases. We can enable 0-D masks if they are needed in the future. See: https://github.com/llvm/llvm-project/issues/116197
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