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authorMin-Yih Hsu <min.hsu@sifive.com>2024-11-12 15:29:40 -0800
committerGitHub <noreply@github.com>2024-11-12 15:29:40 -0800
commit84e95beae980466ffcc555297e0e34d23fca8a76 (patch)
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[RISCV] Update SiFive P600's scheduling model on RVV instructions (#115243)
The biggest change is assigning vector crypto instructions to the correct processor resource. The majority of these changes are guided by our RVV-capable llvm-exegesis.
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