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authorRyan Prichard <rprichard@google.com>2018-09-26 20:50:38 +0000
committerRyan Prichard <rprichard@google.com>2018-09-26 20:50:38 +0000
commitb7c8d2d405fb418e1c02004a8be3e541383ac2a1 (patch)
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parent83e360a42720fee14e9886fb0c39d3dc9965a789 (diff)
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[AArch64] Fix range check of R_AARCH64_TLSLE_ADD_TPREL_HI12
Summary: An AArch64 LE relocation is a positive ("variant 1") offset. This relocation is used to write the upper 12 bits of a 24-bit offset into an add instruction: add x0, x0, :tprel_hi12:v1 The comment in the ARM docs for R_AARCH64_TLSLE_ADD_TPREL_HI12 is: "Set an ADD immediate field to bits [23:12] of X; check 0 <= X < 2^24." Reviewers: javed.absar, espindola, ruiu, peter.smith, zatrazz Reviewed By: ruiu Subscribers: emaste, arichardson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D52525 llvm-svn: 343144
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