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author | Craig Topper <craig.topper@sifive.com> | 2023-12-20 09:52:02 -0800 |
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committer | GitHub <noreply@github.com> | 2023-12-20 09:52:02 -0800 |
commit | b03f0c596a180399f7730ed75d78055c81b3d771 (patch) | |
tree | 724c3176eef850c380067c54af95464fe8f14f6d /clang/test/Misc | |
parent | 7a87ff64e1fe970adcc41b7fc664fb5fd8410a68 (diff) | |
download | llvm-b03f0c596a180399f7730ed75d78055c81b3d771.zip llvm-b03f0c596a180399f7730ed75d78055c81b3d771.tar.gz llvm-b03f0c596a180399f7730ed75d78055c81b3d771.tar.bz2 |
[RISCV] Add sifive-p450 CPU. (#75760)
This is an out of order core with no vector unit. More information:
https://www.sifive.com/cores/performance-p450-470
Scheduler model and other tuning will come in separate patches.
Diffstat (limited to 'clang/test/Misc')
-rw-r--r-- | clang/test/Misc/target-invalid-cpu-note.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index e840a92..48e9f05 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -85,7 +85,7 @@ // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}} +// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}} // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' @@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} |