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| author | Jim Lin <jim@andestech.com> | 2025-03-04 16:49:24 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-04 16:49:24 +0800 |
| commit | 03505a004ff6909c46d6b8c498a9ffccd47d88a0 (patch) | |
| tree | 746a19d5c27e87e443b97eb387f36ee0064231bb /clang/test/AST/ast-print-openacc-declare-construct.cpp | |
| parent | 47fb9c4bb9b057ab45c5228937a2c1fbf51c4f72 (diff) | |
| download | llvm-03505a004ff6909c46d6b8c498a9ffccd47d88a0.zip llvm-03505a004ff6909c46d6b8c498a9ffccd47d88a0.tar.gz llvm-03505a004ff6909c46d6b8c498a9ffccd47d88a0.tar.bz2 | |
[RISCV] Enable scalable loop vectorization for fmax/fmin reductions with f16/bf16 type for zvfhmin/zvfbfmin (#129629)
This PR enable scalable loop vectorization for fmax and fmin reductions
with f16/bf16 type when only zvfhmin/zvfbfmin are enabled.
After https://github.com/llvm/llvm-project/pull/128800, we can promote
the fmax/fmin reductions with f16/bf16 type to f32 reductions for
zvfhmin/zvfbfmin.
Diffstat (limited to 'clang/test/AST/ast-print-openacc-declare-construct.cpp')
0 files changed, 0 insertions, 0 deletions