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| author | Victor Campos <victor.campos@arm.com> | 2020-03-09 13:29:37 +0000 |
|---|---|---|
| committer | Victor Campos <victor.campos@arm.com> | 2020-03-11 10:19:27 +0000 |
| commit | 8a12553223180246eeafaa0fa7bfa11e834d34b6 (patch) | |
| tree | 257ff9d07715da873e2edae55256a8af5aa1edc0 /clang/lib | |
| parent | 9304decdeeb89390256d0193bc3bd40fb40e6bd5 (diff) | |
| download | llvm-8a12553223180246eeafaa0fa7bfa11e834d34b6.zip llvm-8a12553223180246eeafaa0fa7bfa11e834d34b6.tar.gz llvm-8a12553223180246eeafaa0fa7bfa11e834d34b6.tar.bz2 | |
[ARM] Improve codegen of volatile load/store of i64
Summary:
Instead of generating two i32 instructions for each load or store of a volatile
i64 value (two LDRs or STRs), now emit LDRD/STRD.
These improvements cover architectures implementing ARMv5TE or Thumb-2.
The code generation explicitly deviates from using the register-offset
variant of LDRD/STRD. In this variant, the register allocated to the
register-offset cannot be reused in any of the remaining operands. Such
restriction seems to be non-trivial to implement in LLVM, thus it is
left as a to-do.
Reviewers: dmgreen, efriedma, john.brawn, nickdesaulniers
Reviewed By: efriedma, nickdesaulniers
Subscribers: danielkiss, alanphipps, hans, nathanchance, nickdesaulniers, vvereschaka, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70072
Diffstat (limited to 'clang/lib')
0 files changed, 0 insertions, 0 deletions