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| author | Zi Xuan Wu <zixuan.wu@linux.alibaba.com> | 2021-11-18 10:22:21 +0800 |
|---|---|---|
| committer | Zi Xuan Wu <zixuan.wu@linux.alibaba.com> | 2021-11-18 11:14:27 +0800 |
| commit | 24d1673c8b9ba32083ad3fa8d587a9fab8b637ad (patch) | |
| tree | b023515cdf2749f846fac654ba8f59d823dc266f /clang/lib/Serialization/ModuleManager.cpp | |
| parent | c26dbc4ab4b891c978f8eac76e892af5765e6ac3 (diff) | |
| download | llvm-24d1673c8b9ba32083ad3fa8d587a9fab8b637ad.zip llvm-24d1673c8b9ba32083ad3fa8d587a9fab8b637ad.tar.gz llvm-24d1673c8b9ba32083ad3fa8d587a9fab8b637ad.tar.bz2 | |
[llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
Not only RISCV but also other target such as CSKY, there are compressed instructions mixed with normal instructions.
To reuse the basic infra to compress/uncompress and predict instruction, we need reconstruct the RISCVCompressInstEmitter
and make it more general and suitable for other target.
Differential Revision: https://reviews.llvm.org/D113475
Diffstat (limited to 'clang/lib/Serialization/ModuleManager.cpp')
0 files changed, 0 insertions, 0 deletions