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| author | Jonathan Thackray <jonathan.thackray@arm.com> | 2025-05-19 17:15:03 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-05-19 17:15:03 +0100 |
| commit | e8a2ce1e9c9db26f2adf4ea6c65eea0299d3a211 (patch) | |
| tree | 1aeb58d62f86e12cbaed2a3fa23ae6dd0de40ccf /clang/lib/Serialization/ModuleCache.cpp | |
| parent | 35a9631279268b6d3d0f0826da0c09e78db6529a (diff) | |
| download | llvm-e8a2ce1e9c9db26f2adf4ea6c65eea0299d3a211.zip llvm-e8a2ce1e9c9db26f2adf4ea6c65eea0299d3a211.tar.gz llvm-e8a2ce1e9c9db26f2adf4ea6c65eea0299d3a211.tar.bz2 | |
[AArch64] When printing SYS aliases, use explicit `NeedsReg` flag from tablegen (NFC) (#140484)
Currently, when printing SYS aliases, the first instruction operand is
compared with the string constant "all" to decide if a register needs to
be parsed as the next operand.
For example, `TLBI VMALLE1IS` contains "all" so no register is expected,
but `TLBI IPAS2E1IS` doesn't match, so a register is expected.
Future AArch64 SYS aliases won't always match this pattern, so use the
(already provided) explicit `NeedsReg` bit flag provided in tablegen to
check if a register is required to be parsed. This is already used by
the code in `AArch64InstPrinter.cpp`, so now we are consistent in this
source file too.
No test files have been changed, since this is a non-functional change,
and all AArch64 test cases continue to pass after this change.
Diffstat (limited to 'clang/lib/Serialization/ModuleCache.cpp')
0 files changed, 0 insertions, 0 deletions