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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-04-16 13:10:56 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-16 13:10:56 +0530 |
| commit | 11857bef8a5fdfb8ab65971c3da6593c6076ff62 (patch) | |
| tree | 87d96689d4b89a2ec6adc947c2b7b3fa5df83f50 /clang/lib/Sema/SemaModule.cpp | |
| parent | bf0de88696095342aaa58e5e0a0105403d5ebd5e (diff) | |
| download | llvm-11857bef8a5fdfb8ab65971c3da6593c6076ff62.zip llvm-11857bef8a5fdfb8ab65971c3da6593c6076ff62.tar.gz llvm-11857bef8a5fdfb8ab65971c3da6593c6076ff62.tar.bz2 | |
[RISCV] Add basic ISel patterns for Xqcisls instructions (#135918)
This patch adds basic instruction selection patterns for generating the
scaled load/store instructions that are a part of the Qualcomm uC
Xqcisls vendor extension.
Diffstat (limited to 'clang/lib/Sema/SemaModule.cpp')
0 files changed, 0 insertions, 0 deletions