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| author | Amara Emerson <aemerson@apple.com> | 2020-06-22 16:25:49 -0700 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2020-06-23 19:23:47 -0700 |
| commit | fceadbcb335da23d0a9beba8c4080a3e4222a385 (patch) | |
| tree | 1feb4e939e8bc413100ff7af933fa3a546bc3f34 /clang/lib/Sema/DeclSpec.cpp | |
| parent | a2caa3b61497b6be8c8b77823d0fd62b4be1f177 (diff) | |
| download | llvm-fceadbcb335da23d0a9beba8c4080a3e4222a385.zip llvm-fceadbcb335da23d0a9beba8c4080a3e4222a385.tar.gz llvm-fceadbcb335da23d0a9beba8c4080a3e4222a385.tar.bz2 | |
[AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.
There's more smarts in AArch64ISelLowering that we don't have yet, but this
change incrementally improves some of the more common patterns. I think future
iterations will want to use some combination of PostLegalizerCombiner and the
selector to catch the other cases.
Differential Revision: https://reviews.llvm.org/D82340
Diffstat (limited to 'clang/lib/Sema/DeclSpec.cpp')
0 files changed, 0 insertions, 0 deletions