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| author | Amara Emerson <amara@apple.com> | 2020-11-13 23:08:47 -0800 |
|---|---|---|
| committer | Amara Emerson <amara@apple.com> | 2020-11-16 10:50:46 -0800 |
| commit | 0b6090699ab542cde24be1565b4d97dbad153cba (patch) | |
| tree | 2390e2e95872142d84427643066c48165dbbe5ff /clang/lib/Sema/DeclSpec.cpp | |
| parent | b877c35d4b2cc67f7c3d96698fcd3845683ce5e2 (diff) | |
| download | llvm-0b6090699ab542cde24be1565b4d97dbad153cba.zip llvm-0b6090699ab542cde24be1565b4d97dbad153cba.tar.gz llvm-0b6090699ab542cde24be1565b4d97dbad153cba.tar.bz2 | |
[AArch64][GlobalISel] Look through a G_ZEXT when trying to match shift-extended register offsets.
The G_ZEXT in these cases seems to actually come from a combine that we do but
SelectionDAG doesn't. Looking through it allows us to match "uxtw #2" addressing
modes.
Differential Revision: https://reviews.llvm.org/D91475
Diffstat (limited to 'clang/lib/Sema/DeclSpec.cpp')
0 files changed, 0 insertions, 0 deletions