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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-03-11 11:17:34 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-03-11 11:17:49 +0000 |
| commit | b3b4727a3e7e170189e58ee8a6409112839a87b0 (patch) | |
| tree | ab7ca331da490425af1770eee8f0f3af50d55176 /clang/lib/Lex/ModuleMap.cpp | |
| parent | 6d5603e2d22041c4873da4daebab3386a462c3e0 (diff) | |
| download | llvm-b3b4727a3e7e170189e58ee8a6409112839a87b0.zip llvm-b3b4727a3e7e170189e58ee8a6409112839a87b0.tar.gz llvm-b3b4727a3e7e170189e58ee8a6409112839a87b0.tar.bz2 | |
[X86] Replace (most) X86ISD::SHLD/SHRD usage with ISD::FSHL/FSHR generic opcodes (PR39467)
For i32 and i64 cases, X86ISD::SHLD/SHRD are close enough to ISD::FSHL/FSHR that we can use them directly, we just need to account for the operand commutation for SHRD.
The i16 SHLD/SHRD case is annoying as the shift amount is modulo-32 (vs funnel shift modulo-16), so I've added X86ISD::FSHL/FSHR equivalents, which matches the generic implementation in all other terms.
Something I'm slightly concerned with is that ISD::FSHL/FSHR legality is controlled by the Subtarget.isSHLDSlow() feature flag - we don't normally use non-ISA features for this but it allows the DAG combines to continue to operate after legalization in a lot more cases.
The X86 *bits.ll changes are all affected by the same issue - we now have a "FSHR(-1,-1,amt) -> ROTR(-1,amt) -> (-1)" simplification that reduces the dependencies enough for the branch fall through code to mess up.
Differential Revision: https://reviews.llvm.org/D75748
Diffstat (limited to 'clang/lib/Lex/ModuleMap.cpp')
0 files changed, 0 insertions, 0 deletions