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| author | Gaëtan Bossu <41161573+gbossu@users.noreply.github.com> | 2024-10-25 20:19:22 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-25 11:19:22 -0700 |
| commit | a0c318938a528cfbef509a2516b36dd2411a52b6 (patch) | |
| tree | e195f2b36c31453cbd290edc9a60901e37670c7d /clang/lib/Lex/ModuleMap.cpp | |
| parent | f4db221258cb44a8f9804ce852c0403328de39b2 (diff) | |
| download | llvm-a0c318938a528cfbef509a2516b36dd2411a52b6.zip llvm-a0c318938a528cfbef509a2516b36dd2411a52b6.tar.gz llvm-a0c318938a528cfbef509a2516b36dd2411a52b6.tar.bz2 | |
[CodeGen][NFC] Properly split MachineLICM and EarlyMachineLICM (#113573)
Both are based on MachineLICMBase, and the functionality there is
"switched" based on a PreRegAlloc flag. This commit is simply about
trusting the original value of that flag, defined by the `MachineLICM`
and `EarlyMachineLICM` classes.
The `PreRegAlloc` flag used to be overwritten it based on MRI.isSSA(),
which is un-reliable due to how it is inferred by the MIRParser. I see
that we can now define isSSA in MIR (thanks @gargaroff ), meaning the
fix isn’t really needed anymore, but redefining that flag still feels
wrong.
Note that I'm looking into upstreaming more changes to MachineLICM, see
[the discourse
thread](https://discourse.llvm.org/t/extending-post-regalloc-machinelicm/82725).
Diffstat (limited to 'clang/lib/Lex/ModuleMap.cpp')
0 files changed, 0 insertions, 0 deletions