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| author | Craig Topper <craig.topper@sifive.com> | 2022-08-30 11:59:37 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-08-30 12:22:46 -0700 |
| commit | 893f5e95e254e000222513b5fea1921f1796145c (patch) | |
| tree | a1fa256eb418e0773ca8b899fa37480133246b21 /clang/lib/Lex/ModuleMap.cpp | |
| parent | fd1f8c85f2c0b989d1ac3a05b920f5b5fa355645 (diff) | |
| download | llvm-893f5e95e254e000222513b5fea1921f1796145c.zip llvm-893f5e95e254e000222513b5fea1921f1796145c.tar.gz llvm-893f5e95e254e000222513b5fea1921f1796145c.tar.bz2 | |
[RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros.
We can use srliw to shift out the trailing bits and slli to shift
back in zeros. The sign extend of srliw will 0 the upper 32 bits
since we will be shifting a 0 into bit 31.
Diffstat (limited to 'clang/lib/Lex/ModuleMap.cpp')
0 files changed, 0 insertions, 0 deletions