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| author | Craig Topper <craig.topper@sifive.com> | 2025-01-27 22:40:05 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-27 22:40:05 -0800 |
| commit | ea9993a9a3500c3fdda3faa731c458389458eaa6 (patch) | |
| tree | a72a95310aac4bc8563396b087435fc07681737a /clang/lib/Frontend/ModuleDependencyCollector.cpp | |
| parent | 085f7fb560ee08a4d78a51dbf247ea816f8515a7 (diff) | |
| download | llvm-ea9993a9a3500c3fdda3faa731c458389458eaa6.zip llvm-ea9993a9a3500c3fdda3faa731c458389458eaa6.tar.gz llvm-ea9993a9a3500c3fdda3faa731c458389458eaa6.tar.bz2 | |
[RISCV] Add P550 scheduler model. (#124639)
P550 falls between P450 and P650. It has 1 additional FEX pipe over
P450. Mul and cpop latency are 3 instead of 2.
I've set the MicroOpBufferSize to 96 instead of 56 based on the ROB size
measurement from
https://chipsandcheese.com/p/inside-sifives-p550-microarchitecture I
believe we set this value too low for P450 and P650 and should update
them in a separate PR.
Diffstat (limited to 'clang/lib/Frontend/ModuleDependencyCollector.cpp')
0 files changed, 0 insertions, 0 deletions