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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-02-08 17:31:06 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-02-08 17:39:19 +0000 |
commit | bef25ae297d6d246bf0fa8667c8b08f9d5e8dae7 (patch) | |
tree | 76ebfc87a4f2d96683983ee8c0492405bdf1559b /clang/lib/Frontend/ModuleDependencyCollector.cpp | |
parent | af97edff70b0d9cb89729dc0d8af1d1ea101686e (diff) | |
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[X86] X86FixupVectorConstants - use explicit register bitwidth for the loaded vector instead of using constant pool bitwidth
Fixes #81136 - we might be loading from a constant pool entry wider than the destination register bitwidth, affecting the vextload scale calculation.
ConvertToBroadcastAVX512 doesn't yet set an explicit bitwidth (it will default to the constant pool bitwidth) due to difficulties in looking up the original register width through the fold tables, but as we only use rebuildSplatCst this shouldn't cause any miscompilations, although it might prevent folding to broadcast if only the lower bits match a splatable pattern.
Diffstat (limited to 'clang/lib/Frontend/ModuleDependencyCollector.cpp')
0 files changed, 0 insertions, 0 deletions