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| author | Luo, Yuanke <yuanke.luo@intel.com> | 2022-05-04 12:39:45 +0800 |
|---|---|---|
| committer | Luo, Yuanke <yuanke.luo@intel.com> | 2022-05-05 10:44:57 +0800 |
| commit | 373ce147602cb2007ac861bc1956c16f473780a6 (patch) | |
| tree | 1ee4304b6558ce3972d0efad5c3e68ffb7acaa75 /clang/lib/Frontend/CreateInvocationFromCommandLine.cpp | |
| parent | dc66897d4cd54749725e4cc189a88933fe3593b1 (diff) | |
| download | llvm-373ce147602cb2007ac861bc1956c16f473780a6.zip llvm-373ce147602cb2007ac861bc1956c16f473780a6.tar.gz llvm-373ce147602cb2007ac861bc1956c16f473780a6.tar.bz2 | |
[X86][AMX] Replace PXOR instruction with SET0 in AMX pre config.
To generate zero value, the PXOR instruction need 3 operands that is
tied to the same vreg. If is not good in SSA form and with undef value
two address instruction pass may convert
`%0:vr128 = PXORrr undef %0, undef %0`
to `%1:vr128 = PXORrr undef %1:vr128(tied-def 0), undef %0:vr128`.
It is not expected.
It can be simplified to SET0 instruction which only take 1 destination
operand. It should be more friendly to two address instruction pass and
register allocation pass.
`%0:vr128 = V_SET0`
Also add AVX1 code path so that it is consistant to other code.
Differential Revision: https://reviews.llvm.org/D124903
Diffstat (limited to 'clang/lib/Frontend/CreateInvocationFromCommandLine.cpp')
0 files changed, 0 insertions, 0 deletions