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| author | Craig Topper <craig.topper@sifive.com> | 2021-01-25 16:17:42 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-01-25 16:37:21 -0800 |
| commit | ea87cf2acd82e435e485c6e1884b54ba7427a54d (patch) | |
| tree | f8a937eb51469b366d87858a88db4b866d8a4b06 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | f9b6fd269b6fd2b085c3537b6730a02503430ef0 (diff) | |
| download | llvm-ea87cf2acd82e435e485c6e1884b54ba7427a54d.zip llvm-ea87cf2acd82e435e485c6e1884b54ba7427a54d.tar.gz llvm-ea87cf2acd82e435e485c6e1884b54ba7427a54d.tar.bz2 | |
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
RISCV has to use 2 shifts for (i64 (zext_inreg X, i32)), but we
can use addiw rd, rs1, x0 for sext_inreg. We already understood this
when type legalizing i32 seteq/ne on rv64. But this transform in
SimplifySetCC would sometimes undo it.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D95289
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions