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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2021-05-18 17:05:49 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2021-05-27 11:49:37 -0400 |
| commit | e892705d74c7366a1404a3b3471001edaa7659f8 (patch) | |
| tree | df4195aa799aae48616fa09418d96354da9d33ae /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 7922ff601094585c4b46b2640b7d07986f722c1b (diff) | |
| download | llvm-e892705d74c7366a1404a3b3471001edaa7659f8.zip llvm-e892705d74c7366a1404a3b3471001edaa7659f8.tar.gz llvm-e892705d74c7366a1404a3b3471001edaa7659f8.tar.bz2 | |
GlobalISel: Do not change register types in lowerLoad
Adjusting the load register type is a widenScalar type action, not a
lowering. lowerLoad should be reserved for operations that change the
memory access size, such as unaligned load decomposition. With this
trying to adjust the register type, it was hard to avoid infinite
loops in the legalizer. Adds a bandaid to avoid regressing a few
AArch64 tests, but I'm not sure what the exact condition is and
there's probably a cleaner way to do this.
For AMDGPU this regresses handling of some cases for unaligned loads,
but the way this is currently working is a pretty ugly hack.
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions