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| author | Craig Topper <craig.topper@sifive.com> | 2022-02-13 18:56:18 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-02-13 19:09:26 -0800 |
| commit | e72fe654b72349d93b86a3dae28fc5bcce970f85 (patch) | |
| tree | 5998f4323b4aadc6b294ab9d4c377adb5f683d00 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | b2f5164deb0e7bd27603022772dfba8814a389b1 (diff) | |
| download | llvm-e72fe654b72349d93b86a3dae28fc5bcce970f85.zip llvm-e72fe654b72349d93b86a3dae28fc5bcce970f85.tar.gz llvm-e72fe654b72349d93b86a3dae28fc5bcce970f85.tar.bz2 | |
[DAGCombiner] Use getShiftAmountConstant in DAGCombiner::foldSelectOfConstants.
This enables fshl to be matched earlier on X86
%6 = lshr i32 %3, 1
%7 = select i1 %4, i32 -2147483648, i32 0
%8 = or i32 %6, %7
X86 uses i8 for shift amounts. SelectionDAGBuilder creates the
ISD::SRL with an i8 shift type. DAGCombiner turns the select into
an ISD::SHL. Prior to this patch it would use i32 for the shift
amount. fshl matching failed because the shift amounts have different
types. LegalizeDAG fixes the ISD::SHL shift amount to i8. This
allowed fshl matching to succeed.
With this patch, the ISD::SHL will be created with an i8 shift
amount. This allows the fshl to match immediately.
No test case beause we still end up with a fshl either way.
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions