diff options
| author | Craig Topper <craig.topper@gmail.com> | 2020-10-19 11:50:47 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2020-10-19 12:53:14 -0700 |
| commit | e28376ec28b9034a35e01c95ccb4de9ccc6c4954 (patch) | |
| tree | 2db03e7473de758169558457eb2ef606072a06d7 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | ae3625d7526f50c39784ca6b0532a74c059516c2 (diff) | |
| download | llvm-e28376ec28b9034a35e01c95ccb4de9ccc6c4954.zip llvm-e28376ec28b9034a35e01c95ccb4de9ccc6c4954.tar.gz llvm-e28376ec28b9034a35e01c95ccb4de9ccc6c4954.tar.bz2 | |
[X86] Add i32->float and i64->double bitcast pseudo instructions to store folding table.
We have pseudo instructions we use for bitcasts between these types.
We have them in the load folding table, but not the store folding
table. This adds them there so they can be used for stack spills.
I added an exact size check so that we don't fold when the stack slot
is larger than the GPR. Otherwise the upper bits in the stack slot
would be garbage. That would be fine for Eli's test case in PR47874,
but I'm not sure its safe in general.
A step towards fixing PR47874. Next steps are to change the ADDSSrr_Int
pseudo instructions to use FR32 as the second source register class
instead of VR128. That will keep the coalescer from promoting the
register class of the bitcast instruction which will make the stack
slot 4 bytes instead of 16 bytes.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D89656
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions