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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2025-08-07 16:13:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-07 16:13:34 -0700 |
| commit | dddeb07c2ea9bc4e507d3bd34980fa6e9513ed9f (patch) | |
| tree | 6a37496d71a908154a0d25026248b0a283beb217 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | cb2d56ce960714ce6fce39e8b846326969a30c2d (diff) | |
| download | llvm-dddeb07c2ea9bc4e507d3bd34980fa6e9513ed9f.zip llvm-dddeb07c2ea9bc4e507d3bd34980fa6e9513ed9f.tar.gz llvm-dddeb07c2ea9bc4e507d3bd34980fa6e9513ed9f.tar.bz2 | |
[AMDGPU] Restrict packed math FP32 instructions to read only one SGPR per operand on gfx12+ (#152465)
Sec. 4.6.7.1 of the gfx1250 SPG states that if an SGPR is used
as an operand, only one SGPR will be read for both the low and high
operations. As a result, the corresponding bits in `op_sel` and
`op_sel_hi` must be the same when the operand is an SGPR.
Co-authored-by: Tian, Shilei <Shilei.Tian@amd.com>
Co-authored-by: Tian, Shilei <Shilei.Tian@amd.com>
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions