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| author | Craig Topper <craig.topper@intel.com> | 2020-02-11 11:04:47 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-02-11 11:24:25 -0800 |
| commit | d7de7ac370181ec0acb42fa2e4085c870868c4e0 (patch) | |
| tree | e3dc110c4f050f8d08e9427c5a18ac0f64b8eb4b /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 9220bbc9091d5804a8321618cf73903c0ec9493f (diff) | |
| download | llvm-d7de7ac370181ec0acb42fa2e4085c870868c4e0.zip llvm-d7de7ac370181ec0acb42fa2e4085c870868c4e0.tar.gz llvm-d7de7ac370181ec0acb42fa2e4085c870868c4e0.tar.bz2 | |
[X86] Raise the latency for VectorImul from 4 to 5 in Skylake scheduler models
Based on uops.info these should have 5 cycle latency as they did on Haswell/Broadwell. I have no additional internal information from Intel.
This was also shown as a discrepancy in the spreadsheet that was sent with an early llvm-dev post about llvm-exegesis.
It also matches Agner Fog.
Differential Revision: https://reviews.llvm.org/D74357
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions