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| author | James Chesterman <James.Chesterman@arm.com> | 2025-02-18 09:08:47 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-18 09:08:47 +0000 |
| commit | d4a0848dc6678bc4ce8c74855a818dfc8c30a088 (patch) | |
| tree | 20983012ec487b5c91f237de72ed55bebf769019 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 88dd372d673c7e6967c93aa2879f0ef04fc7ac20 (diff) | |
| download | llvm-d4a0848dc6678bc4ce8c74855a818dfc8c30a088.zip llvm-d4a0848dc6678bc4ce8c74855a818dfc8c30a088.tar.gz llvm-d4a0848dc6678bc4ce8c74855a818dfc8c30a088.tar.bz2 | |
[SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (#125207)
Add signed and unsigned PARTIAL_REDUCE_MLA ISD nodes. Add command line
argument (aarch64-enable-partial-reduce-nodes) that indicates whether the
intrinsic experimental_vector_partial_ reduce_add will be transformed
into the new ISD node. Lowering with the new ISD nodes will, for now,
always be done as an expand.
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions