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| author | Victor Campos <Victor.Campos@arm.com> | 2019-12-16 14:22:15 +0000 |
|---|---|---|
| committer | Victor Campos <Victor.Campos@arm.com> | 2019-12-19 11:23:01 +0000 |
| commit | bbcf1c3496ce2bd1ed87e8fb15ad896e279633ce (patch) | |
| tree | 58ccd7772e2d72f39c1af6b02f729a5a66be61ad /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | eca0c97a6bca49b493f3387dbd88ad60c852320f (diff) | |
| download | llvm-bbcf1c3496ce2bd1ed87e8fb15ad896e279633ce.zip llvm-bbcf1c3496ce2bd1ed87e8fb15ad896e279633ce.tar.gz llvm-bbcf1c3496ce2bd1ed87e8fb15ad896e279633ce.tar.bz2 | |
[ARM] Improve codegen of volatile load/store of i64
Summary:
Instead of generating two i32 instructions for each load or store of a volatile
i64 value (two LDRs or STRs), now emit LDRD/STRD.
These improvements cover architectures implementing ARMv5TE or Thumb-2.
Reviewers: dmgreen, efriedma, john.brawn
Reviewed By: efriedma
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70072
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions