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| author | Hsiangkai Wang <kai.wang@sifive.com> | 2021-02-09 14:43:10 +0800 |
|---|---|---|
| committer | Hsiangkai Wang <kai.wang@sifive.com> | 2021-02-09 15:52:04 +0800 |
| commit | a2d19bad07454ae7936d8f2b8482e24d57954fc4 (patch) | |
| tree | 235ddc384a62478e17c9dc02ce1e16751a20d9ff /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 1473b00cf814fae5dbd3fe4f48f6a75a0b2b9094 (diff) | |
| download | llvm-a2d19bad07454ae7936d8f2b8482e24d57954fc4.zip llvm-a2d19bad07454ae7936d8f2b8482e24d57954fc4.tar.gz llvm-a2d19bad07454ae7936d8f2b8482e24d57954fc4.tar.bz2 | |
[RISCV] Use whole register load/store for generic load/store.
In vector v0.10, there are whole vector register load/store
instructions. I suggest to use the whole register load/store
instructions for generic load/store for scalable vector types. It could
save up vset{i}vl{i} for these load/store.
For fractional LMUL, I keep to use vle{eew}.v/vse{eew}.v instructions to
load/store partial vector registers.
Differential Revision: https://reviews.llvm.org/D95853
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions