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authorChristian Ulmann <christianulmann@gmail.com>2024-04-05 08:25:36 +0200
committerGitHub <noreply@github.com>2024-04-05 08:25:36 +0200
commit974f1ee58da1c51c547eaf5c7007a215fd286c68 (patch)
treecd8bc285e940383d189ada726b8a81b84f343459 /clang/lib/Frontend/CompilerInvocation.cpp
parent1c683eb324aea08b2f9de26cac27532da8a0f7e3 (diff)
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[MLIR][LLVM][Mem2Reg] Relax type equality requirement for load and store (#87637)
This commit relaxes Mem2Reg's type equality requirement for the LLVM dialect's load and store operations. For now, we only allow loads to be promoted if the reaching definition can be casted into a value of the target type. For stores, the same conversion casting check is applied and we ensure that their result is properly casted to the type of the memory slot. This is necessary to satisfy assumptions of the general mem2reg pass, as it creates block arguments with the types of the memory slot. This relands https://github.com/llvm/llvm-project/pull/87504
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