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author | Shengchen Kan <shengchen.kan@intel.com> | 2024-01-19 00:05:44 +0800 |
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committer | Shengchen Kan <shengchen.kan@intel.com> | 2024-01-19 00:19:55 +0800 |
commit | 8bc7c0a058ff0e6495b8e7e4dd850e646228506b (patch) | |
tree | 32c703e0c4bcdaf403ae224010471fe51f9eee10 /clang/lib/Frontend/CompilerInvocation.cpp | |
parent | 3044d754855c339319b041e579c569d4faf32b62 (diff) | |
download | llvm-8bc7c0a058ff0e6495b8e7e4dd850e646228506b.zip llvm-8bc7c0a058ff0e6495b8e7e4dd850e646228506b.tar.gz llvm-8bc7c0a058ff0e6495b8e7e4dd850e646228506b.tar.bz2 |
[X86] Fix failures on EXPENSIVE_CHECKS builds
Error message
```
*** Bad machine code: Illegal virtual register for instruction ***
- function: test__blsi_u32
- basic block: %bb.0 (0x7a61208)
- instruction: %5:gr32 = MOV32r0 implicit-def $eflags
- operand 0: %5:gr32
Expected a GR32_NOREX2 register, but got a GR32 register
```
Reported by RKSimon in #77433
The failure is b/c compiler emits a MOV32r0 with operand GR32 when
fast-isel is enabled.
```
// X86FastISel.cpp
Register SrcReg = fastEmitInst_(X86::MOV32r0, &X86::GR32RegClass)
```
However, before this patch, compiler only allows GR32_NOREX operand
b/c MOV32r0 is a pseudo instruction. In this patch, we relax the
register class of the operand to GR32 b/c MOV32r0 is always expanded
to XOR32rr, which can use EGPR.
The bug was not introduced by #77433 but caught by it.
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions