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| author | David Green <david.green@arm.com> | 2020-04-26 21:58:58 +0100 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2020-04-27 10:13:29 +0100 |
| commit | 8807139026b64ac40163bb255dad38a1d8054f08 (patch) | |
| tree | 5ee52571b1ab14874a1891878ee6827bab4c3f22 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 1a0d466081318adfc356917fccc5116f9031ef7e (diff) | |
| download | llvm-8807139026b64ac40163bb255dad38a1d8054f08.zip llvm-8807139026b64ac40163bb255dad38a1d8054f08.tar.gz llvm-8807139026b64ac40163bb255dad38a1d8054f08.tar.bz2 | |
[ARM] Only produce qadd8b under hasV6Ops
When compiling for a arm5te cpu from clang, the +dsp attribute is set.
This meant we could try and generate qadd8 instructions where we would
end up having no pattern. I've changed the condition here to be hasV6Ops
&& hasDSP, which is what other parts of ARMISelLowering seem to use for
similar instructions.
Fixed PR45677.
Differential Revision: https://reviews.llvm.org/D78877
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions