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| author | Sander de Smalen <sander.desmalen@arm.com> | 2023-11-01 16:15:47 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2023-11-01 16:29:44 +0000 |
| commit | 7dc20abed0d121b7492b3da261aca9d9ea4d0ad1 (patch) | |
| tree | 16e7b2a6174b8bd903a9a86e33b667be1b896687 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 9220e0e647a1e4fbfb0f990117f88f171f9f2f65 (diff) | |
| download | llvm-7dc20abed0d121b7492b3da261aca9d9ea4d0ad1.zip llvm-7dc20abed0d121b7492b3da261aca9d9ea4d0ad1.tar.gz llvm-7dc20abed0d121b7492b3da261aca9d9ea4d0ad1.tar.bz2 | |
[AArch64] Fix spillfill-sve.mir with expensive checks.
This fixes an issue introduced by PR #70679.
Using constrainRegClass() is not strong enough to actually force
the use of a register to be a PPR register class. It will need an
actual COPY to do the conversion.
The downside is that this introduces an extra register, which is an
issue we may want to fix at a later point using a custom copy operation
where the register allocator uses the same register when it can.
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions