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| author | Sebastian Neubauer <sebastian.neubauer@amd.com> | 2021-02-04 09:56:36 +0100 |
|---|---|---|
| committer | Sebastian Neubauer <sebastian.neubauer@amd.com> | 2021-02-04 09:56:36 +0100 |
| commit | 6c59dc474dcc6db6daa1dad8bccc098bce4942ee (patch) | |
| tree | 721ce838e53fff5e48c0b57a4dea0aed117d911e /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 5eec9a380a24bf0611c676b5da4933949c787a6b (diff) | |
| download | llvm-6c59dc474dcc6db6daa1dad8bccc098bce4942ee.zip llvm-6c59dc474dcc6db6daa1dad8bccc098bce4942ee.tar.gz llvm-6c59dc474dcc6db6daa1dad8bccc098bce4942ee.tar.bz2 | |
[AMDGPU] Save all lanes for reserved VGPRs
When SGPRs are spilled to VGPRs, they can overwrite any lane. We need
to preserve the value of inactive lanes in function calls, so we save
the register even if it is marked as caller saved.
Also, teach buildPrologSpill to work when no registers are free like in
CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir and update the comment on
findScratchNonCalleeSaveRegister as it is not used anymore to realign
the stack pointer since D95865.
Differential Revision: https://reviews.llvm.org/D95946
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions