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| author | Sanjay Patel <spatel@rotateright.com> | 2020-08-26 15:21:54 -0400 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2020-08-26 15:23:08 -0400 |
| commit | 54a5dd485c4d04d142a58c9349ada0c897cbeae6 (patch) | |
| tree | 632df33a6b50036f02976bc51bf75d808cdea632 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | c6c292da910578bdec76616c606da2d79b730667 (diff) | |
| download | llvm-54a5dd485c4d04d142a58c9349ada0c897cbeae6.zip llvm-54a5dd485c4d04d142a58c9349ada0c897cbeae6.tar.gz llvm-54a5dd485c4d04d142a58c9349ada0c897cbeae6.tar.bz2 | |
[DAGCombiner] allow store merging non-i8 truncated ops
We have a gap in our store merging capabilities for shift+truncate
patterns as discussed in:
https://llvm.org/PR46662
I generalized the code/comments for this function in earlier commits,
so we only need ease the type restriction and adjust the address/endian
checking to make this work.
AArch64 lets us switch endian to make sure that patterns are matched
either way.
Differential Revision: https://reviews.llvm.org/D86420
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions