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| author | QingShan Zhang <qshanz@cn.ibm.com> | 2020-09-12 02:42:22 +0000 |
|---|---|---|
| committer | QingShan Zhang <qshanz@cn.ibm.com> | 2020-09-12 02:42:22 +0000 |
| commit | 528554c39b098e2d9a9c7ec51c77717aa07db2a2 (patch) | |
| tree | a2003a8f72da8e7a394472b856aa141f801e9173 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 0e0d93e2f09a3e84cee0e77f0f2510001c2f064a (diff) | |
| download | llvm-528554c39b098e2d9a9c7ec51c77717aa07db2a2.zip llvm-528554c39b098e2d9a9c7ec51c77717aa07db2a2.tar.gz llvm-528554c39b098e2d9a9c7ec51c77717aa07db2a2.tar.bz2 | |
[PowerPC] Set the mayRaiseFPException for FCMPUS/FCMPUD
From ISA, fcmpu will raise the Floating-Point Invalid Operation
Exception (SNaN) if either of the operands is a Signaling NaN by setting
the bit VXSNAN. But the instruction description didn't set the
mayRaiseFPException which might have impact on the scheduling or some
backend optimization.
Reviewed By: qiucf
Differential Revision: https://reviews.llvm.org/D83937
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions