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| author | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2021-08-27 00:05:41 -0400 |
|---|---|---|
| committer | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2021-09-01 02:55:45 -0400 |
| commit | 4dab15288d69c9002c98473588232d6ecbd7d29e (patch) | |
| tree | e5bac00f41b45cebdb9991011f4c9d20d0ae7570 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 5eaebd5d649ad7209ddef37ea7118e262f755a14 (diff) | |
| download | llvm-4dab15288d69c9002c98473588232d6ecbd7d29e.zip llvm-4dab15288d69c9002c98473588232d6ecbd7d29e.tar.gz llvm-4dab15288d69c9002c98473588232d6ecbd7d29e.tar.bz2 | |
[AMDGPU] Introduce RC flags for vector register classes
Configure and use the TSFlags in TargetRegisterClass to
have unique flags for VGPR and AGPR register classes.
The vector register class queries like `hasVGPRs` will
now become more efficient with just a bitwise operation.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D108815
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions