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| author | Petar Avramovic <Petar.Avramovic@amd.com> | 2021-01-20 10:09:59 +0100 |
|---|---|---|
| committer | Petar Avramovic <Petar.Avramovic@amd.com> | 2021-01-20 10:37:09 +0100 |
| commit | 4ab704d62820396af5bd4a4322a5cbc2700a7ec3 (patch) | |
| tree | 4334c67196eda2374bc24bb7a75f33399d320c70 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 2aeaaf841b58b2a6721f9271ae897e392fd0b357 (diff) | |
| download | llvm-4ab704d62820396af5bd4a4322a5cbc2700a7ec3.zip llvm-4ab704d62820396af5bd4a4322a5cbc2700a7ec3.tar.gz llvm-4ab704d62820396af5bd4a4322a5cbc2700a7ec3.tar.bz2 | |
[AMDGPU][MC] Add tfe disassembler support MIMG opcodes
With tfe on there can be a vgpr write to vdata+1.
Add tablegen support for 5 register vdata store.
This is required for 4 register vdata store with tfe.
Differential Revision: https://reviews.llvm.org/D94960
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions