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| author | Ayke van Laethem <aykevanlaethem@gmail.com> | 2020-02-05 15:04:47 +0100 |
|---|---|---|
| committer | Ayke van Laethem <aykevanlaethem@gmail.com> | 2020-06-10 20:55:47 +0200 |
| commit | 1ba7809793913daae4e15d8ca6acbf80db21816d (patch) | |
| tree | fab6296262ffc31f7a1cdd7370012d784b307d11 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 6e1eee6034f7220f170cb78b8a1334cff2b8b911 (diff) | |
| download | llvm-1ba7809793913daae4e15d8ca6acbf80db21816d.zip llvm-1ba7809793913daae4e15d8ca6acbf80db21816d.tar.gz llvm-1ba7809793913daae4e15d8ca6acbf80db21816d.tar.bz2 | |
[AVR] Implement disassembly support for I/O instructions
The in, out, and sbi/cbi family of instructions seem to require a custom
decoder. I'm not exactly sure why and would prefer to convince TableGen
to provide the correct decoders for these, but I can't seem to convince
it to do so. They simply disassemble without any operands.
Differential Revision: https://reviews.llvm.org/D74049
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
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