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| author | Craig Topper <craig.topper@sifive.com> | 2022-06-20 18:58:23 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-06-20 18:58:24 -0700 |
| commit | 16d3a82de53dab4bb5ed468aff92df276f8a6e39 (patch) | |
| tree | 132f06120b4e08d38a13382ddef5fe5d710b772e /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 6c951c5ee6d0b848877cb8ac7a9cb2a9ef9ebbb5 (diff) | |
| download | llvm-16d3a82de53dab4bb5ed468aff92df276f8a6e39.zip llvm-16d3a82de53dab4bb5ed468aff92df276f8a6e39.tar.gz llvm-16d3a82de53dab4bb5ed468aff92df276f8a6e39.tar.bz2 | |
[RISCV] Add merge operand to RISCVISD::VRGATHER*_VL nodes.
Use it in place of VSELECT_VL+VRGATHER*_VL.
This simplifies the isel patterns.
Overall, I think trying to match select+op to create masked instructions
in isel doesn't scale. We either need to do it in DAG combine, pre-isel
peepole, or post-isel peephole. I don't yet know which is the right
answer, but for this case it seemed best to be able to request the
masked form directly from lowering.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D128023
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions