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| author | Craig Topper <craig.topper@sifive.com> | 2022-05-11 10:48:12 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-05-11 10:49:16 -0700 |
| commit | 078174278574761edfd557908af59c67aa7b303e (patch) | |
| tree | 9ebd885d19212265d028e06dc5e861c3dc9c9f62 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 72925d98bf928431e430a49a0504bda8d7d0d184 (diff) | |
| download | llvm-078174278574761edfd557908af59c67aa7b303e.zip llvm-078174278574761edfd557908af59c67aa7b303e.tar.gz llvm-078174278574761edfd557908af59c67aa7b303e.tar.bz2 | |
[RISCV] Add a DAG combine to pre-promote (i32 (and (srl X, Y), 1)) with Zbs on RV64.
Type legalization will want to turn (srl X, Y) into RISCVISD::SRLW,
which will prevent us from using a BEXT instruction.
I don't think there is any precedent for type promotion checking
users to decide how to promote. Instead, I've added this DAG combine to
do it before type legalization.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D124109
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions