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author | Saiyedul Islam <Saiyedul.Islam@amd.com> | 2020-04-27 08:26:03 +0530 |
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committer | Sameer Sahasrabuddhe <sameer.sahasrabuddhe@amd.com> | 2020-04-27 09:39:03 +0530 |
commit | 06bdffb2bb45d8666ec86782d21214ef545a71fd (patch) | |
tree | bc5b3122b1f730d6ca2e51bb96da520e2e18ef6a /clang/lib/Frontend/CompilerInvocation.cpp | |
parent | 84eff8cef61df89c54e73f99baa3ba3cf03b5e55 (diff) | |
download | llvm-06bdffb2bb45d8666ec86782d21214ef545a71fd.zip llvm-06bdffb2bb45d8666ec86782d21214ef545a71fd.tar.gz llvm-06bdffb2bb45d8666ec86782d21214ef545a71fd.tar.bz2 |
[AMDGPU] Expose llvm fence instruction as clang intrinsic
Expose llvm fence instruction as clang builtin for AMDGPU target
__builtin_amdgcn_fence(unsigned int memoryOrdering, const char *syncScope)
The first argument of this builtin is one of the memory-ordering specifiers
__ATOMIC_ACQUIRE, __ATOMIC_RELEASE, __ATOMIC_ACQ_REL, or __ATOMIC_SEQ_CST
following C++11 memory model semantics. This is mapped to corresponding
LLVM atomic memory ordering for the fence instruction using LLVM atomic C
ABI. The second argument is an AMDGPU-specific synchronization scope
defined as string.
Reviewed By: sameerds
Differential Revision: https://reviews.llvm.org/D75917
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions