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authorSaiyedul Islam <Saiyedul.Islam@amd.com>2020-04-27 08:26:03 +0530
committerSameer Sahasrabuddhe <sameer.sahasrabuddhe@amd.com>2020-04-27 09:39:03 +0530
commit06bdffb2bb45d8666ec86782d21214ef545a71fd (patch)
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parent84eff8cef61df89c54e73f99baa3ba3cf03b5e55 (diff)
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[AMDGPU] Expose llvm fence instruction as clang intrinsic
Expose llvm fence instruction as clang builtin for AMDGPU target __builtin_amdgcn_fence(unsigned int memoryOrdering, const char *syncScope) The first argument of this builtin is one of the memory-ordering specifiers __ATOMIC_ACQUIRE, __ATOMIC_RELEASE, __ATOMIC_ACQ_REL, or __ATOMIC_SEQ_CST following C++11 memory model semantics. This is mapped to corresponding LLVM atomic memory ordering for the fence instruction using LLVM atomic C ABI. The second argument is an AMDGPU-specific synchronization scope defined as string. Reviewed By: sameerds Differential Revision: https://reviews.llvm.org/D75917
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