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| author | zhongyunde 00443407 <zhongyunde@huawei.com> | 2024-04-24 04:10:35 -0400 |
|---|---|---|
| committer | vfdff <zhongyunde@huawei.com> | 2024-04-25 08:50:31 +0800 |
| commit | a35d7d7d124172632a9a108f76deba647f4da863 (patch) | |
| tree | 69502d4f7919e36b2782baad262e7a8dec15e6d6 /clang/lib/Frontend/ASTUnit.cpp | |
| parent | d5308949cf884d8e4b971d51a8b4f73584c4adec (diff) | |
| download | llvm-a35d7d7d124172632a9a108f76deba647f4da863.zip llvm-a35d7d7d124172632a9a108f76deba647f4da863.tar.gz llvm-a35d7d7d124172632a9a108f76deba647f4da863.tar.bz2 | |
[AArch64][SelectionDAG] Correct the shift amounts bound
Accord D152827, when the shift amounts is 4 or less, they are
cheap as a move.
Diffstat (limited to 'clang/lib/Frontend/ASTUnit.cpp')
0 files changed, 0 insertions, 0 deletions