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| author | Craig Topper <craig.topper@sifive.com> | 2021-04-27 12:48:44 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-04-27 14:38:16 -0700 |
| commit | ce09dd54e6eca4903bfb1dcb230ba002159f969c (patch) | |
| tree | a164284fb176e9aa22bed4cf4d8b9b354a5f0131 /clang/lib/CodeGen/ObjectFilePCHContainerOperations.cpp | |
| parent | a495b672b7ff90fef9aaa296a1c52e0921e71875 (diff) | |
| download | llvm-ce09dd54e6eca4903bfb1dcb230ba002159f969c.zip llvm-ce09dd54e6eca4903bfb1dcb230ba002159f969c.tar.gz llvm-ce09dd54e6eca4903bfb1dcb230ba002159f969c.tar.bz2 | |
[RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter.
This adds a special operand type that is allowed to be either
an immediate or register. By giving it a unique operand type the
machine verifier will ignore it.
This perturbs a lot of tests but mostly it is just slightly different
instruction orders. Something bad did happen to some min/max reduction
tests. We're spilling vector registers when we weren't before.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D101246
Diffstat (limited to 'clang/lib/CodeGen/ObjectFilePCHContainerOperations.cpp')
0 files changed, 0 insertions, 0 deletions